Medium 6.5Published Nov 9, 2025

CVE-2025-63384A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privile…

Updated under an hour ago (Oct 28, 2026, 9:50 AM ET)

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Exploited in the last 30 days

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

CVSS: 6.5 MEDIUM (v3.1, CISA ADP)CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N
Weakness (CWE): CWE-266
Known exploited: Not in CISA's KEV catalog
EPSS (exploitation in the next 30 days): Not loaded for this CVE
Assigned by: mitre
NVD analysis: Analyzed
Record last updated: Nov 12, 2025
First seen by InfoSec Signals: Oct 9, 2026

Affected products

Affected products

chipsalliance rocketchip chipsalliance:rocketchip	through 1.6	NVD

References

References

https://github.com/chipsalliance/rocket-chip.git	product
https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET	exploit, third-party-advisory

The CVE record on cve.org NVD's entry

The CVE record is authoritative. Products marked “from the name” were identified from the CNA's free-text names, not a CPE, and are matched less certainly. This product uses the NVD API but is not endorsed or certified by the NVD.